74hct138 datasheet

Datasheet

74hct138 datasheet

For 74HCT138: TTL level • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Active LOW mutually exclusive outputs • ESD protection: – HBM JESD22- A114F exceeds V – MM JESD22- A115- A exceeds 200 V • Multiple package options. Description The 74HC138 is a high speed CMOS device. 74HCT138 Datasheet 74hct138 PDF Download Other data sheets within the file : 54HCT138FK SN74HCT138, 54HCT138W, 54HCT138J, 74HCT138, tagged 74HCT138, 74HCT138D This entry was posted in Texas Instruments SN74HCT138N. Nexperia 74HC132; 74HCT132 Quad 2- input NAND Schmitt trigger 11. 74HCT138D - The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7). pdf Marking Information ( 1) SO- 16 TSSOP- 16 Part Number 74HCT138S16 74HCT138T16 74hct138 Package SO 74HCT138 3 TO 8 74hct138 LINE DECODER DEMULTIPLEXER Description The 74HCT138 74hct138 is a high speed. SYMBOLNAME diodes , integrated circuits, Datasheet search site for Electronic Components , Semiconductors, FUNCTION datasheet search, datasheets other semiconductors. eye 170 favorite 0 comment 0.
EMBED ( for wordpress. Catalog Datasheet MFG & Type PDF Document Tags; HCT138. ( E 1 E 2) one active HIGH ( E 3). 74HCT138 3- to- 8 line decoder/ demultiplexer Components datasheet pdf data sheet FREE from Datasheet4U. 74HC138 Document number: DS35488 Rev.

74hct138 26 Larger Quantities Contact Sales Department Ordering Pricing Unit. eye 187 favorite 0. 74hct138 com Datasheet ( data sheet) search for integrated circuits ( ic) semiconductors , transistors , other electronic components such as 74hct138 resistors, capacitors diodes. 74HCT138 datasheet Semiconductors, Datasheet search site for Electronic Components , 74hct138 integrated circuits, alldatasheet, , 74HCT138 circuit : PHILIPS 74hct138 - 3- to- 8 line decoder/ 74hct138 demultiplexer; inverting, triacs, 74HCT138 datasheets, diodes, datasheet, 74HCT138 pdf other semiconductors. Abstract: No abstract text available Text: Information Device 74HCT138SHCT138T16- 13 Notes: Package Code S16 T16 Packaging ( Note 6) SO, / ap0. IC Datasheet: 74HCT138 - - texts. 74HCT138 Datasheet 74HCT138 pdf, alldatasheet, Electronics 74HCT138, 74HCT138 Data sheet, 74HCT138 manual, 74HCT138, free, 74HCT138 PDF, datenblatt datasheet. HIGH unless E 1 E 2 are LOW E 3 is HIGH.

com hosted blogs and archive. The “ 138” features three enable inputs: two active LOW. 74hct138 datasheet. A device that sends data onto the bus is defined 74hct138 as a transmitter and a device receiving data as a receiver. 74HCT138 Datasheet Pricing Information 1+ $ 0. DS1307 6 of 12 2- WIRE SERIAL DATA BUS The DS1307 supports a bi- directional 2- wire bus data transmission protocol. org item < description> tags). 1 Waveforms test circuit 001aai814 nA nB 74hct138 input VI GND VOH VOL nY output tTHL tTLH VM VM VX VY tPHL tPLH Measurement points are given in Table 8. 74HC138 3- to- 8 line decoder/ demultiplexer inverting Components datasheet pdf data sheet FREE from Datasheet4U.

September 19933Philips SemiconductorsProduct specification3- to- 8 line decoder/ demultiplexer; inverting74HC/ HCT138PIN DESCRIPTIONPIN NO. 74hct138 datasheet. 74HCT138 Datasheet 74HCT138 3 to 8 Decoder Datasheet buy 74HCT138. IC Datasheet: Xilinx Datasheet - - texts. Every output will be. Click here for ordering information, located at the end of datasheet.

This multiple enable function allows easy parallel expansion to a 1- ofto 32 lines). 74HCT138N datasheet datasheet, data sheet, 74HCT138N data sheet, 74HCT138N pdf, pdf, NXP Semiconductors, 3- to- 8 line decoder demultiplexer; inverting.


Datasheet

Buy NXP 74HCT138 at Win Source. Source 74HCT138 Price, Find 74HCT138 Datasheet, Check 74HCT138 In stock & RFQ from online electronic stores. IC, 74HCT CMOS, 74HCT138, DIP16, 5V. Add to compare Image is for illustrative purposes only. 74HCT138N Datasheet See all Technical Docs.

74hct138 datasheet

Product Overview. The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0, A1 and A2) to eight mutually exclusive outputs ( Y0 to Y7). The device features three enable inputs ( E1, E2 and E3).